Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device with a delay line for delaying and outputting an input signal.
A synchronous semiconductor memory device such as Double Data Rate Synchronous Dynamic Random Access Memory transfers and receives data to and from an external device, such as a memory controller CTRL, by using an internal clock synchronized with an external clock inputted from the external device.
To stably transfer a data between a memory device and a memory controller, it is important to temporally synchronize the data outputted from the memory device with an external clock transferred from the memory controller to the memory device.
A data is outputted from the memory device in synchronization with an internal clock. The internal clock is transferred to the memory device in synchronization with the external clock in the initial block but the internal clock becomes delayed as it goes through the constituent elements inside the memory device (internal delay time) and thus by the time when the internal clock is outputted out of the memory device, it may not be synchronized with the external clock any more.
Therefore, to stably transfer a data outputted from the memory device, the internal clock should be compensated for the internal delay time when the data is loaded on a bus so that the internal clock is synchronized with the external clock transferred from the memory controller and thus accurately positioned at the edge or center of the external clock.
As mentioned above, the internal clock should be compensated for the internal delay time when the data is loaded on a bus. Herein, the internal clock is a delayed clock obtained as the external clock transferred from the memory controller passes through a delay circuit modeled based on the constituent elements inside the memory device that transfers the data. Since the delay amount of the delay circuit modeled based on the constituent elements inside the memory device that transfers the data cannot be altered, a method of further delaying the phase of the internal clock until the phase of the internal clock is synchronized with the phase of the external clock has been conventionally used.
However, it is difficult to calculate the phase difference between the internal clock and the external clock in advance. Moreover, the phase difference between the internal clock and the external clock may be changed at any time according to the driving environment of the memory device. Therefore, the internal clock is delayed in a delay circuit whose delay amount is freely changed according to a control signal in order to accurately synchronize the phase of the internal clock with the phase of the external clock.
Also, when the driving environment of the memory device is worst, the phase difference between the internal clock and the external clock may reach almost one clock cycle (that is, 1tck). To accurately synchronize the phase of the internal clock with the phase of the external clock while satisfying condition of the worst driving environment, the internal clock is often delayed with a delay circuit having a wide variation of a delay amount which varies according to a control signal.
Therefore, the following delay line that satisfies the above-described conditions of the above-described delay circuit is used to synchronize the phase of the internal with the phase of the external clock.
FIG. 1 is a block diagram illustrating a conventional semiconductor device having delay lines.
Referring to FIG. 1, the conventional semiconductor device having delay lines includes an upper delay line 10 for delaying an input signal IN_SIG, a lower delay line 12 for delaying the input signal IN_SIG, and a delay controller 14 for controlling the delay amounts of the upper delay line 10 and the lower delay line 12. The conventional semiconductor device having delay lines further includes a phase mixer 16 for mixing the phase of a first output signal OUT_SIG1 outputted from the upper delay line 10 and the phase of a second output signal OUT_SIG2 outputted from the lower delay line 12 to thereby generate a final output signal OUT_SIG_F.
In examining the structures of the upper delay line 10 and the lower delay line 12, a plurality of NAND gates are serially coupled and among the plurality of the serially coupled NAND gates, NAND gates of a predetermined interval are designed to receive an input signal IN_SIG. However, to which NAND gate the input signal IN_SIG is to be transferred is determined based on a delay control code CON_1<1>, CON_1<2>, . . . , CON_1<N>, CON_2<1>, CON_2<2>, . . . , CON_2<N>, which is outputted from the delay controller 14.
The operation of the conventional semiconductor device having the above structure will be described herein.
First, referring to FIG. 1, the upper delay line 10 and the lower delay line 12 are designed to have a NAND gate at one of four positions c within the delay line as a NAND gate capable of receiving an applied input signal IN_SIG, among the plurality of NAND gates serially coupled. This is because it is assumed that the delay amount corresponding to two NAND gates is a unit delay amount in FIG. 1.
In other words, the process of generating the final output signal OUT_SIG_F by delaying the input signal IN_SIG includes a process of mixing the phase of the first output signal OUT_SIG1 outputted from the upper delay line 10 and the phase of the second output signal OUT_SIG2 outputted from the lower delay line 12 in the phase mixer 16 to thereby generate and output the final output signal OUT_SIG_F. Therefore, it can be understood that the first output signal OUT_SIG1 outputted from the upper delay line 10 and the second output signal OUT_SIG2 outputted from the lower delay line 12 may be different by the two unit delay amounts (2×unit delay amounts), which corresponds to delays through the four NAND gates, where the delay amount of the final output signal OUT_SIG_F changes by the unit delay amount corresponding to two NAND gates.
This is based on an assumption that the phase mixer 16 mixes the first output signal OUT_SIG1 outputted from the upper delay line 10 and the second output signal OUT_SIG2 outputted from the lower delay line 12 using the same weight. While an operation of changing the delay amount of the final output signal OUT_SIG_F by a delay amount smaller than the unit delay by changing the weight of the phase mixer 16 is performed after the operations of the upper delay line 10 and the lower delay line 12 can be performed, normally, the phase mixer 16 mixes the first output signal OUT_SIG1 outputted from the upper delay line 10 and the second output signal OUT_SIG2 outputted from the lower delay line 12 using the same weight during a process that the delay amounts of the first output signal OUT_SIG1 outputted from the upper delay line 10 and the second output signal OUT_SIG2 outputted from the lower delay line 12 are changed.
In the conventional semiconductor device having delay lines described above, an input signal IN_SIG is transferred to both of the upper delay line 10 and the lower delay line 12 and the phases of the two output signals OUT_SIG1 and OUT_SIG2 outputted from the upper delay line 10 and the lower delay line 12, respectively, are mixed to thereby generate the final output signal OUT_SIG_F. In this way, the delay amount of the final output signal OUT_SIG_F can be changed not only on the basis of the unit delay but also on the basis of a delay amount smaller than the unit delay amount.
To perform this operation, the conventional semiconductor device requires two delay lines, which are the upper delay line 10 and the lower delay line 12 and the input signal IN_SIG should be provided to both of the upper delay line 10 and the lower delay line 12.
In short, the two delay lines 10 and 12 should be driven simultaneously with respect to one input signal IN_SIG. Therefore, there arises a concern that an input driver 18 for driving the two delay lines 10 and 12 for one input signal IN_SIG are large in size.
Also, in examining the structures of the two delay lines 10 and 12 shown in FIG. 1, the two delay lines 10 and 12 operate in a Multiple Input Single Output (MISO) method.
To be specific, the two delay lines 10 and 12 have a structure in which multiple NAND gates corresponding to two unit delay amounts (2×unit delay amounts) selectively receives an input signal IN_SIG and the received input signal IN_SIG is outputted through a NAND gate positioned at the beginning of the two unit delay structures.
Therefore, as the two delay lines 10 and 12 becomes longer and lower, the size of the input driver 18 is increased in order to stably transfer the input signal IN_SIG to multiple NAND gates corresponding to two unit delay amounts (2×unit delay amounts). The increasing size of the input driver 18 raises a concern.
Herein, since the input driver 18 is a circuit which is always turned on while the two delay lines 10 and 12 perform an operation for delaying the input signal IN_SIG, the larger the input driver 18 is, the higher the current consumption becomes.
Also, the increase in the length of the two delay lines 10 and 12 signifies that the length of a line that the input signal IN_SIG passes through becomes long. This means that the loading applied to the input signal IN_SIG is increased, which raises a concern as well.
Moreover, the line through which the two delay lines 10 and 12 pass has a form that it is coupled in parallel to the multiple NAND gates corresponding to the two unit delay amounts (2×unit delay amounts). Therefore, there arises a concern that the gate capacitances of the transistors included in the multiple NAND gates are taken as loads.
As a result, the increase in the length of the two delay lines 10 and 12 leads to an increase in the size of the loads applied to the input signal IN_SIG. The increased load not only inhibits the input signal IN_SIG from being transferred quickly but also adversely affects the signal quality of the input signal IN_SIG.
According to the conventional technology, the increased load not only renders the delay lines unsuitable for a fast response time but also impairs the accuracy. Therefore, the conventional method is not applicable to a semiconductor device with delay lines operating at a high speed.